In recent years, many semiconductor devices having a multilayer wiring structure have been developed. In the multilayer wiring structure, for example, a fin made of silicon may be formed at the bottom of a recess sandwiched by two interlayer films. Furthermore, in such a structure, a silicon-containing film sometimes covers the fin formed at the bottom. There may be a case where the silicon-containing film is removed to form electrodes or the like. Since the multilayer wiring structure is a very fine and complicated structure, the removal of the silicon-containing film does not require an etching stop layer. An isotropic etching technique may be used to remove the silicon-containing film existing in a fine gap. A chemical etching process, for example, a COR (Chemical Oxide Removal) process is suitably used for the removal of the silicon-containing film.
However, since the interlayer film is also formed of a silicon-containing film, there is a possibility that the interlayer film is removed by the COR process and is made thin. If the interlayer film is made thin, for example, the gate length becomes short, which makes it difficult to control the switching in a transistor. This poses a problem that the yield of a semiconductor device deteriorates.